1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to an adjustable strength driver circuit for off chip drivers used in semiconductor memories and a method of adjustment.
2. Description of the Related Art
Semiconductor memories, such as dynamic random access memories (DRAMs), include an off chip driver (OCD) or an output buffer which provide a signal to be sent off the semiconductor chip during operation. A memory chip often includes an array of output buffers to permit simultaneous output of multiple databits. When several of the drivers of the array of buffers are in operation, the rise and/or fall time of the outgoing signals are slowed down. This is true for signals driven off the memory chip. The slow down is caused primarily by power and ground supply noise, and the resulting decrease in a gate to drain voltage (V.sub.gs) and drain to source voltage (V.sub.ds) of driver transistors of the buffer array. The load at the output is driven by less overdrive voltage V.sub.gs and less voltage difference V.sub.ds between source and drain of the driving transistor.
In DRAMs, there are typically between 4 to 32 output buffers, arranged in an array, and having a dedicated power supply. Package parasitics include inductances of a lead frame and a bond wire and capacitive loads including internal and external output loads as indicated in FIG. 1. When, as a worst case, a majority of output buffers have to drive data of a same polarity (either "0" or "1", single-sided), this causes a decrease of V.sub.gs and V.sub.ds. over the driving transistor. This slows down the rising or falling edge of the output signal and results in a lower speed performance of the DRAM. Although the rising or falling edge delay may be compensated for by increasing the width of the driving transistor, this cannot be performed dynamically and may therefore violate maximum slew rates in best cases.
Referring to FIG. 1, a typical output buffer 10 is shown having parasitic load 12 and capacitive loads 13 and 15 associated with lead frame and bond wire. Output buffer 10 includes two driving transistors 14 and 16. Transistor 14 is driven by an n-logic signal while transistor 16 is driven by a p-logic signal. Transistor 14 has a source coupled to a first supply voltage (i.e., VSSD) while transistor 16 has a source coupled to a second supply voltage (VDDQ). When n-logic drives transistor 14 (which is an NFET pull transistor) to drive node OUT low, node 2 will temporarily bounce up (dI/dt noise, i.e., &lt;U=L.E-backward.dI/dt where &lt;U; is voltage variation caused by parasitic inductances L and dI/dt is the derivative of the current with respect to time). This voltage change caused by the inductance is not negligible and may significantly contribute to the decrease in V.sub.gs and V.sub.ds for transistor 14. When a majority of output buffers in an array drive the same data (1's or 0's), this effect is further enhanced and causes a slowing down of the signal's OUT falling edge because V.sub.gs and V.sub.ds decrease further. Output timings become data pattern dependent resulting in reduced timing margins especially when the DRAM chip is operated at high frequencies.
Therefore, a need exists for an output buffer which dynamically adjusts the drive strength according to a data pattern to be output from an array of output buffers in its vicinity.